TDDB30	System Specification, Verification and Validation, 6 ECTS-points /Systemspecifikation verifikation och validering/ Advancement level: C
	Aim: To get basic knowledge in industrial development methods for systems with embedded software. To get knowledge and abilities to specify systems with discrete modeling tools like automatons, flowgraphs and logic. To get knowledge and understanding for how these apecifications can be used to verify that a design satisfies the functional and performance requirements. To get knowledge about methods for system verification/validation using testing. Prerequisites: TDDA47 Real-time and Concurrent Programming or TDDB47 Real-Time Systems Course organization: The course contains 16 hrs lectures, 20 hrs lessons and 24 hrs laborations. Course content: Lectures: Development of systems with embedded software. What is a system specification, formall methods and specification languages. Finite automatons, Petri nets, reachability space, property proving. Data flow diagrams and their properties. To use logic to prove properties, Specification of temporal behaviour. Large, complex systems - problems to prove properties. Testmethods. Lessons: Introduction to the tools that are going to be used in laborations. Examples of specification and modelling langusges. Laborations: Project on case study - using Statemate, RDD-100, and NP-tools. Course literature: Ken Shumate, Marilyn Keller: Software Specification and Design - A Disciplined Approach for Real-Time Systems, Wiley 1992. Handouts.
TEN1	Written examination, 1 p.
PRA1	, 2 p.
UPG1	, 1 p.

Course language is swedish.