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Valid for year : 2014
 
TSIU03 System Design, 8 ECTS credits.
/Systemkonstruktion/

For:   DI   EL  

 

Prel. scheduled hours: 52
Rec. self-study hours: 161

  Area of Education: Technology

Main field of studies: Electrical Engineering

  Advancement level (G1, G2, A): G2

Aim:
  • Design a digital circuit (RTL) that calculates a mathematical function.
  • Analyze the mathematical function calculated by a digital circuit (RTL).
  • Generate VHDL code that describes a digital circuit (RTL).
  • Analyze the digital circuit (RTL) described by a VHDL code.
  • Formulate the requirements for a digital system.
  • Identify the phases and tasks involved in the development of a digital system.
  • Generate, analyze and compare alternative approaches to implement a digital system.
  • Create an implementation of a digital system on an FPGA that fulfills a set of requirements.
  • Apply simulation tools to test, verify and validate a digital system.
  • Describe a digital system and justify that it meets a set of requirements.


    • Prerequisites: (valid for students admitted to programmes within which the course is offered)
    Switching Theory and Logical Design, Computer Hardware and Architecture

    Note: Admission requirements for non-programme students usually also include admission requirements for the programme and threshhold requirements for progression within the programme, or corresponding.
    Organisation:
    The course consist of a series of lectures, laboratory work and a large design project that includes assignments and implementation of a system.
    Course contents:
    Design of complex systems, project organisation, planning and documentation. Problem capture, specification, system design, complexity, partitioning and validation. Use of CAD-CAE tools. Behavioral description using VHDL. System architectures. Automatic synthesis of logic and implementation using FPGA technologies.
    Course literature:
    "VHDL for Logic Synthesis", Andrew Rushton. John Wiley & Sons, 2011 (3rd edition). ISBN-13: 978-0470688472
    "Digital Design: An Embedded Systems Approach Using VHDL", Peter J. Ashenden. Morgan Kaufmann, 2007. ISBN-13: 978-0123695284
    Examination:
    Oral and written presentation of project work
    Laboratory work
    		 5 ECTS
    3 ECTS
     
    Grades are given as 'Fail' or 'Pass'


    Course language is English.
    Department offering the course: ISY.
    Director of Studies: Tomas Svensson
    Examiner: Mario Garrido
    Link to the course homepage at the department


    Course Syllabus in Swedish

    Linköping Institute of Technology
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    Contact: TFK , val@tfk.liu.se
    Last updated: 11/06/2014