| TSTE12 |
Design of Digital Systems , 6 ECTS credits.
/Konstruktion av digitala system/
For:
D
ED
ELE
IT
Y
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Prel. scheduled
hours: 44
Rec. self-study hours: 116
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Area of Education: Technology
Main field of studies: Electrical Engineering, Computer Engineering
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Advancement level
(G1, G2, A): A
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Aim:
The course includes methods and tools for design and implementation of complex electronic systems. The emphasis is put on the design process.
- Design executable models using a hardware descripition language
- Model digital systems at different abstraction levels using an hardware description language
- Perform a project task following a project model
- Use logic synthesis and modelling tools to create prototypes and applications in FPGA and VLSI
- Use VHDL for modelling and synthesis of advanced digital systems
- Know about how IP blocks works and are used in FPGA and VLSI designs
- Know about how FPGA circuits function and can be used
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Prerequisites: (valid for students admitted to programmes within which the course is offered)
Basic courses in digital circuits. Basic courses in programming.
Note: Admission requirements for non-programme students usually also include admission requirements for the programme and threshhold requirements for progression within the programme, or corresponding.
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Supplementary courses:
System Design, CDIO
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Organisation:
Besides lectures, the course includes a laboration series and a small project.
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Course contents:
Design of complex digital systems. Problem definition, specification, design process. Complexity, partitioning, and validation. Hardware description languages, introduction to VHDL.
Behavioral descriptions, modeling techniques, time delays. Test benches and verification methods. Hard real-time systems. Computational properties of algorithms, methods for scheduling, resource allocation and assignment. Synthesis of optimal architectures. Tools for design and simulation. Description of the design process for logic synthesis, optimization for VLSI
implementation. Fast prototyping using FPGA.
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Course literature:
K. L. Short, VHDL for Engineers, Prentice Hall 1997
Svensson T., Krysander C., Projektmodellen LIPS, Studentlitteratur, 2011
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Examination: |
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Oral presentation of project report
One laboratory course with assignement
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4 ECTS
2 ECTS
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Grades are given as â?~Failâ?T or â?~Passâ?T. |
Course language is Swedish/English.
Department offering the course: ISY.
Director of Studies: Tomas Svensson
Examiner: Kent Palmkvist
Link to the course homepage at the department
Course Syllabus in Swedish
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