| TDDB30 | Embedded systems simulation and verification, 6 ECTS credits. /Inbyggda systems simulering och verifiering/ |
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Area of Education: Subject area: |
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| Advancement level
(A-D): C
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| Aim: To get basic knowledge in industrial development methods for systems with embedded software specially systems which include mechanics, electronics, hydraulics in addition to software. To understand the importance of requirements capture/management for such systems, and the tracing of requirements to different types of subsystems. To get familiar with specifying systems using discrete modeling tools like finite automata,flow graphs and logic. To get an understanding for how these specifications can be used to verify that a design satisfies the functional and performance requirements. To get an overview about methods for system verification/validation using testing |
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| Prerequisites: (valid for students admitted to programmes within which the course is offered) Real-time systems (eg. TDDA47, TDDB47) and basic course in automatic control. Note: Admission requirements for non-programme students usually also include admission requirements for the programme and threshhold requirements for progression within the programme, or corresponding. |
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| Organisation: The course contains introductory lectures, tutorials to prepare for use of tools in the labs, and practical work in the labs as well as (optional) homeworks and report. |
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| Course contents: Lectures: Development of systems with embedded software. Different phases of systems engineering process and standards, and the relation to software engineering. Tools for modelling systems: Finite automata, data flow diagrams and specification languages - discrete as well as hybrid (discrete/continuous). Use of logic to prove system properties. Tutorials: Introduction to the tools used in the labs, for example: requirements management in CORE, design specification in Statemate/Rhapsody (UML), and logik-based verification tools. |
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| Course literature: Systems Engineering: Coping with complexity. R. Stevens, K. Jackson, P. Brook, S. Arnold, Prentice Hall, 1998. Handouts. |
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| Examination: | |||
| Requirements-tracing laboratory and functional design specification Verification lab with a logic based tool Obligatory assignment to get higher than minimum grade |
3 p 1 p 0 p |
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Course language is Swedish. Department offering the course: IDA. Director of Studies: sas-sr@ida.liu.se Examiner: Simin Nadjm-Tehrani Link to the course homepage at the department Course Syllabus in Swedish |
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