| TSTE70 | Design of Digital Systems , 7,5 ECTS credits. /Konstruktion av digitala system/ |
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Prel. scheduled
hours: 78 |
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Area of Education: Technology Subject area: Electrical Engineering/Computer Engineering |
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| Advancement level
(A-D): C
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| Aim: The course includes methods and tools for design and implementation of complex electronic systems. The emphasis is put on the design process. The specification of large complex systems must be executable to avoid interpretation errors and to enable performance estimations. The description must then be partitioned into smaller and more detailed descriptions down to a level that allows a mapping to hardware. VHDL is a language used to describe the digital system. Models using increasing levels of details can be built and mixed as well as testbenches used to validate every new model. VHDL is also well suited for logic synthesis from a description at the RTL level. It is however important that the designer is well aware of the principles these tools follows and what results to expect. Hands on experience of the synthesis tools are therefore important to appreciate the problems that may arise. Programmable circuits such as FPGA is increasingly used to replace ASICs as well as for verification of a design in advance of an ASIC manufacturing. |
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| Prerequisites: (valid for students admitted to programmes within which the course is offered) Basic courses in digital circuits. Basic courses in programming. Note: Admission requirements for non-programme students usually also include admission requirements for the programme and threshhold requirements for progression within the programme, or corresponding. |
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| Supplementary courses: TSTE02 System Design, CDIO |
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| Organisation: Besides lectures, the course includes a laboration series and a small project. |
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| Course contents: Design of complex digital systems. Problem definition, specification, design process. Complexity, partitioning, and validation. Hardware description languages, introduction to VHDL. Behavioral descriptions, modeling techniques, time delays. Test benches and verification methods. Hard real-time systems. Computational properties of algorithms, methods for scheduling, resource allocation and assignment. Synthesis of optimal architectures. Tools for design and simulation. Description of the design process for logic synthesis, optimization for VLSI implementation. Fast prototyping using FPGA. |
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| Course literature: Armstrong J., Gray F. G.: ?VHDL design representation and synthesis?, Prentice-Hall 2000 |
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| Examination: | |||
| Oral presentation of project report One laboratory course |
3,5 p 1,5 p |
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| Grades are given as â?~Failâ?T or â?~Passâ?T. | |||
Course language is Swedish/English. Department offering the course: ISY. Director of Studies: Tomas Svensson Examiner: Kent Palmkvist Link to the course homepage at the department Course Syllabus in Swedish |
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